1. Field of the Invention
The invention relates to simulation of semiconductor chips. More specifically, the invention relates to a method and an apparatus for simulating phase lock loops (PLLs) in integrated circuits.
2. Related Art
Most integrated circuits include one or more phase locked loops (PLL) for clock synthesis, clock and data recovery circuits, or frequency synthesis circuits. When integrated circuits ran at relatively low frequencies (clock speeds), timing jitters within the PLLs were not significant and were generally ignored. However, with increasing frequency as well as larger process variation (from advanced manufacturing techniques), the timing jitters of PLLs have become problematic. Specifically, the timing jitters may cause failure of an integrated circuit for various timing issues. Thus, to properly simulate an integrated circuit the timing jitters of any phase locked loops within the integrated circuit must also be accurately simulated.
Phase lock loops are too complicated to be simulated directly. Thus, analysis and simulation of phase locked loops are performed by dividing the PLL into functional sub-blocks. Because timing jitters are related to phase noise, the phase noise of each sub-block of the PLL is computed separately. The phase noise of the sub-blocks are then combined to obtain the phase noise of the PLL. The phase noise of the PLL is then converted to PLL timing jitter values.
FIG. 1(a) illustrates the functional sub-block of a phase locked loop 120 and a reference oscillator 110. Specifically, the functional sub-blocks of phase locked loop 120 include a phase detector 121, a charge pump 123, a loop filter 125, a voltage controlled oscillator 127, and a divider 129. The construction and function of phase locked loops are well known thus, only a brief functional description of phase locked loop 120 is provided. Specifically, reference oscillator 110 provides an input clock signal IN to phase locked loop 120, which generates an output clock signal OUT having a frequency that is N (an integer) times greater than the frequency of input clock signal IN. Internally, output signal OUT is divided by DIVIDER 129 to produce clock signal OUT/N, which has a frequency equal to the frequency of output clock signal OUT divided by N. Phase detector 121 receives both input clock signal IN and clock signal OUT/N. Phase detector 121 controls charge pump 123 based on whether the clock edges of clock signal OUT/N are ahead or behind the clock edges of input clock signal CLK. Charge pump 123 controls voltage controlled oscillator 127 through loop filter 125. When the clock edge of clock signal OUT/N is ahead of the clock edge of input clock signal IN, phase detector 121 causes charge pump 123 to decrease the frequency of voltage controlled oscillator 127. Conversely, when the clock edge of clock signal OUT/N is behind the clock edge of input clock signal IN, phase detector 121 causes charge pump 123 to increase the speed of voltage controlled oscillator 127. Thus, the frequency of output clock signal OUT is maintained at approximately N times the frequency of input signal IN.
However, the method of calculating timing jitter described above fails when the phase noise simulation of any sub-block fails. Many sub-blocks of the PLL are very difficult to simulate. In general “digital circuits” having input/output waveforms with sharp transitions and/or sharp corners are difficult to simulate. Thus, phase detectors, frequency dividers (with high divide-by ratios) as well as voltage controlled oscillators in combination with frequency dividers are the most difficult to simulate.
In general, the simulation of the sub-blocks of the PLL involve solving a system of non-linear equations for the voltages and currents in the sub-blocks of the PLL. The method to create the system of non-linear equations for a particular PLL is well known and not described herein. For example, Phase-Locked Loops: Theory and Applications by John L. Stensby, (1997) describes the process for creating the system of non-linear equations for a PLL. In general, the system of non-linear equations represent Kirchhoff's current law in the frequency domain, which states that the sum of the currents entering a node equal the sum of the currents exiting the node. Solving the system of non-linear equation involves finding a residual value (i.e. the amount by which Kirchhoff's current law is violated) to a satisfactorily low level.
A harmonic balance method is used to solve the system of non-linear equation. FIG. 1(b) illustrates harmonic balance system 150 having a linear system construction unit 153, a preconditioner 155, a linear system solver 157, and a non-linear system calculation unit 159. Harmonic balance system 150 receives a system of non-linear equations 151 representing the PLL sub-block being simulated and produces solution 160 using a dual iterative method. Harmonic balance systems are well known in the art and thus only described briefly herein. Specifically, linear system construction unit 153 uses Newton's method to construct a system of linear equations, which are used to calculate the Fourier coefficients of the solution for the system of non-linear equations. Newton's method is an iterative process that begins with an initial guess and tries to converge to a solution. Specifically, if the system of non-linear equations is represented by F(x)=0, where F is a matrix, and x is a vector. The system of linear equations used in the Newton method is J*d=−F, where J is a Jacobian matrix that is the first derivative of F(x), F is the residual and d is the Newton correction vector, which must be derived. For clarity and ease of understanding the system of linear equations is represented as A*x=b, where A is the Jacobian Matrix J, b is equal to −F, and x is a vector equivalent to the vector d.
The system of linear equations is solved using an internal iterative solver (typically a Krylov Solver, such as the generalized minimal residual method (GMRES)) represented by linear system solver 157. Linear system solver 157 attempts to calculate the vector x that satisfies the equation A*x=b; by calculating an approximation vector x_app, so that a residual is lower than a linear system accuracy threshold LSAT. Specifically the residual for linear system solver 157 is equal to the norm of A*x_app−b. However, linear system solver 157 may not be able to solve or would take too long to solve most of system of linear equations generated by Newton's method. Thus, a preconditioner 155 conditions the system of linear equations to assist linear system solver 157. Specifically, preconditioner 155 creates a first preconditioned set of linear equations and linear system solver 157 generates an approximate solution to the first preconditioned set of linear equations. Then preconditioner 155 and linear system solver 157 and repeatedly generates approximate preconditioned sets of linear equations and generates approximate solutions for each preconditioned sets of linear equations to converge on a adequate solution to a preconditioned set of linear equations. The solution is then converted into a solution to the set of linear conditions (non-preconditioned). If an appropriate vector x, is found, linear system solver 157 provides the vector x to non-linear system calculation unit 159 which uses vector x to generate an approximate solution to the system of non-linear equations. If the approximate solution satisfies a non-linear system accuracy threshold NLSAT than the approximate solution is provided as solution 160. Otherwise, the approximate solution is used as the starting point for another iteration by linear system construction unit 153. However, even with preconditioner 155, linear system solver 157 might still not be able to solve the system of linear equations in a reasonable amount of time.
As explained above, the digital sub-blocks of phase lock loops are extremely difficult to simulate. The difficulty results in very slow convergence or even divergence in linear system solver 157 even with the assistance of preconditioner 155. Hence there is a need for a method and system for rapidly simulating phase locked loops.